1. Field of the Invention
The present invention relates to an electronic component embedded substrate and a method for manufacturing the same, and particularly relates to an electronic component embedded substrate wherein an electronic component is embedded in a substrate main body and a method for manufacturing the same.
2. Description of the Related Art
In these years, as semiconductor elements with higher operating frequency have been mounted on semiconductor devices, stabilization of the power supply voltage to the semiconductor elements is becoming necessary. To meet such a need, an electronic component embedded substrate is proposed wherein an electronic component (e.g. capacitor element) is embedded in a semiconductor substrate on which a semiconductor element is mounded.
In the meantime, with the increase of mounting density of semiconductor elements, the pitch of electrode pads formed on the semiconductor elements is being made smaller. However, it is difficult to form wiring patterns on conventional common printed wiring boards with the pitch as small as the pitch of the electrode pads formed on the semiconductor elements. Therefore, the common printed wiring boards are becoming unusable as substrates for mounting semiconductor elements.
Due to such circumstances, the use of multilayer wiring boards called built-up printed wiring boards is increasing. In a multilayer wiring board, a printed wiring board is used as a core layer, and built-up layers and wiring layers are laminated on both faces of the printed wiring board. The wiring layers are interconnected through vias. The term “built-up layer” used herein indicates a layer (a single layer) which is formed with a built-up method, and on the surface of which a wiring layer is formed.
As disclosed in, for example, Patent Document 1, in order to embed an electronic component such as a capacitor element into a multilayer wiring board of this type, the electronic component is incorporated into one of multiple built-up layers.
FIG. 1 is a cross-sectional view illustrating an example of a related-art electronic component embedded substrate 1. The electronic component embedded substrate 1 comprises a core substrate 2, an electronic component 5, and built-up layers 6. The core substrate 2 is, for example, a resin substrate, having wires 3 on upper and lower faces thereof.
The electronic component 5 is, for example, a capacitor element or a semiconductor element, which is bonded to one of the faces (the upper face in the example shown in FIG. 1) of the core substrate 2 with an adhesive agent 4. The built-up layers 6 are formed on the upper and lower faces of the core substrate 2, so the electronic component 5 is incorporated in the built-up layer 6 formed on the upper face of the core substrate 2.
The upper built-up layer 6 is provided with electrode vias 8, through vias 9, and wires 10. The electrode vias 8 are configured to electrically connect the wires 3 formed on the upper face of the core substrate 2 to the wires 10 formed on an upper face of the upper built-up layer 6. The through vias 9 are configured to electrically connect electrodes 7 formed on the electronic component 5 to the wires 10.
Solder resists 11 are formed on surfaces of the built-up layers 6 formed on both faces of the core substrate 2. Openings are formed at predetermined positions of the solder resists 11 such that the wires 10 can have external connections.
[Patent Document 1] Japanese Patent Laid-Open Publication No. 2003-197809, also published as U.S. Patent Application Publication No. 2003/0116843
In such a electronic component embedded substrate 1 in which the core substrate 2 is provided, the electronic component 5 is fixed to either one of the upper face and the lower face of the core substrate 2 and incorporated in one of the built-up layers 6 formed on the same side. With this configuration, however, a center plane of the electronic component 5 does not coincide with the center plane of the electronic component embedded substrate 1.
More specifically, there is a distance (indicate by an arrow H) between the center plane CE1 of the electronic component embedded substrate 1 in a thickness direction (indicated by arrows Z1 and Z2 in FIG. 1) and the center plane CE2 of the electronic component 5 in the thickness direction.
The electronic component 5 is made of a material, such as ceramic and silicon, different from the material (resin) of the core substrate 2 and the built-up layers 6. That is, the electronic component 5 has a thermal expansion coefficient different from the core substrate 2 and the built-up layers 6. Therefore, when the electronic component 5 is embedded in the core substrate 2 with a distance between the center plane CE1 of the electronic component embedded substrate 1 and the center plane CE2 of the electronic component 5, an imbalanced thermal expansion within the electronic component embedded substrate 1 causes warpage in the electronic component embedded substrate 1. For example, experience shows that if the substrate size of the electronic component embedded substrate 1 is 7×10 mm, a warpage of 120 μm occurs. This size of warpage is large enough to make it difficult to have the electronic component embedded substrate 1 in practical use.